A home-made 16-bit processor core with a performance roughly on par with a MOS 6502 or WDC 65816. It is a MISC architecture processor.
Instructions were laid out in memory like so:
15 12 11 8 7 4 3 0 +--------+--------+--------+--------+ | Opcode | Opcode | Opcode | Opcode | | A | B | C | D | +--------+--------+--------+--------+
The processor takes one memory cycle to fetch an instruction word. Following that, it spends the next (up to) four clock cycles executing instructions. Instructions are executed from A to D.
So as to not waste unnecessary time, the processor would detect when the remaining instructions are NOPs; if so, it would fetch the next instruction word. Thus, instruction timing would vary between two cycles and five cycles total.
Some instructions take literal data; for example, a CALL instruction would use the opcode slots B, C, and D as an immediate displacement field.
| Opcode | Mnemonic | Purpose | Notes |
|---|---|---|---|
| 0 | NOP | No operation. | |
| 1 | LIT | Push 16-bit literal onto stack. | Takes operand from next word in instruction stream. |
| 2 | FWM | Fetch Word from Memory | |
| 3 | SWM | Store Word to Memory | |
| 4 | ADD | Add two words | |
| 5 | AND | AND two words bit-wise | |
| 6 | XOR | XOR two words bit-wise | |
| 7 | ZGO | IF 2nd top == 0, GOTO top of stack. | |
| 8 | |||
| 9 | |||
| A | FBM | Fetch Byte from Memory | |
| B | SBM | Store Byte to Memory | |
| C | LCALL | Local Subroutine Call | Uses slots B-D as displacement. |
| D | ICALL | Indirect Subroutine Call | Takes address from top of stack. |
| E | GO | Takes address from top of stack. | |
| F | NZGO | IF 2nd top != 0, GOTO top of stack. |
See the actual data sheet documentation for it up on GitHub.